In an existing array substrate of a liquid crystal display device, a thin film transistor has a passivation layer (PVX) 1 covering thereon, and a pixel electrode 7 is provided on the passivation layer 1 and connected to a drain 8 of the thin film transistor through a via 19 in the passivation layer 1, as shown in FIG. 1.
The via 19 in the passivation layer 1 is formed by an etching process. The via 19 has a larger upper end and a smaller lower end due to the characteristics of the etching process, and thus has a slope angle α which is an angle between the upper surface of a substrate 9 and a sidewall of the via. Since an upper surface of the drain 8 is parallel to the upper surface of the substrate 9, the slope angle α is shown as an angle between the upper surface of the drain 8 and the sidewall of the via. The slope angle α formed by an existing etching process is so large (i.e., a sidewall of the via being approximately perpendicular to the upper surface of the substrate 9) that the pixel electrode 7 is prone to break (as shown by a cross in FIG. 1) at a position of the via 19, causing the pixel electrode 7 to be unable to transmit a signal. As a result, problems such as poor display occur.